bcec8b0b21
This is from the upstream library commit id 3326535126e435f1ba647885ce43a8f0f3d317eb, corresponding to Chromium 88.0.4290.1.
177 lines
9.3 KiB
C
177 lines
9.3 KiB
C
/*
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* Copyright (c) 2013 The WebRTC project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include "common_audio/signal_processing/include/signal_processing_library.h"
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static int16_t coefTable_7[] = {
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4, 256, 8, 128, 12, 384, 16, 64,
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20, 320, 24, 192, 28, 448, 36, 288,
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40, 160, 44, 416, 48, 96, 52, 352,
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56, 224, 60, 480, 68, 272, 72, 144,
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76, 400, 84, 336, 88, 208, 92, 464,
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100, 304, 104, 176, 108, 432, 116, 368,
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120, 240, 124, 496, 132, 264, 140, 392,
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148, 328, 152, 200, 156, 456, 164, 296,
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172, 424, 180, 360, 184, 232, 188, 488,
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196, 280, 204, 408, 212, 344, 220, 472,
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228, 312, 236, 440, 244, 376, 252, 504,
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268, 388, 276, 324, 284, 452, 300, 420,
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308, 356, 316, 484, 332, 404, 348, 468,
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364, 436, 380, 500, 412, 460, 444, 492
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};
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static int16_t coefTable_8[] = {
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4, 512, 8, 256, 12, 768, 16, 128,
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20, 640, 24, 384, 28, 896, 32, 64,
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36, 576, 40, 320, 44, 832, 48, 192,
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52, 704, 56, 448, 60, 960, 68, 544,
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72, 288, 76, 800, 80, 160, 84, 672,
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88, 416, 92, 928, 100, 608, 104, 352,
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108, 864, 112, 224, 116, 736, 120, 480,
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124, 992, 132, 528, 136, 272, 140, 784,
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148, 656, 152, 400, 156, 912, 164, 592,
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168, 336, 172, 848, 176, 208, 180, 720,
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184, 464, 188, 976, 196, 560, 200, 304,
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204, 816, 212, 688, 216, 432, 220, 944,
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228, 624, 232, 368, 236, 880, 244, 752,
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248, 496, 252, 1008, 260, 520, 268, 776,
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276, 648, 280, 392, 284, 904, 292, 584,
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296, 328, 300, 840, 308, 712, 312, 456,
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316, 968, 324, 552, 332, 808, 340, 680,
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344, 424, 348, 936, 356, 616, 364, 872,
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372, 744, 376, 488, 380, 1000, 388, 536,
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396, 792, 404, 664, 412, 920, 420, 600,
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428, 856, 436, 728, 440, 472, 444, 984,
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452, 568, 460, 824, 468, 696, 476, 952,
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484, 632, 492, 888, 500, 760, 508, 1016,
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524, 772, 532, 644, 540, 900, 548, 580,
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556, 836, 564, 708, 572, 964, 588, 804,
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596, 676, 604, 932, 620, 868, 628, 740,
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636, 996, 652, 788, 668, 916, 684, 852,
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692, 724, 700, 980, 716, 820, 732, 948,
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748, 884, 764, 1012, 796, 908, 812, 844,
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828, 972, 860, 940, 892, 1004, 956, 988
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};
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void WebRtcSpl_ComplexBitReverse(int16_t frfi[], int stages) {
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int l;
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int16_t tr, ti;
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int32_t tmp1, tmp2, tmp3, tmp4;
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int32_t* ptr_i;
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int32_t* ptr_j;
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if (stages == 8) {
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int16_t* pcoeftable_8 = coefTable_8;
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__asm __volatile (
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".set push \n\t"
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".set noreorder \n\t"
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"addiu %[l], $zero, 120 \n\t"
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"1: \n\t"
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"addiu %[l], %[l], -4 \n\t"
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"lh %[tr], 0(%[pcoeftable_8]) \n\t"
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"lh %[ti], 2(%[pcoeftable_8]) \n\t"
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"lh %[tmp3], 4(%[pcoeftable_8]) \n\t"
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"lh %[tmp4], 6(%[pcoeftable_8]) \n\t"
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"addu %[ptr_i], %[frfi], %[tr] \n\t"
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"addu %[ptr_j], %[frfi], %[ti] \n\t"
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"addu %[tr], %[frfi], %[tmp3] \n\t"
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"addu %[ti], %[frfi], %[tmp4] \n\t"
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"ulw %[tmp1], 0(%[ptr_i]) \n\t"
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"ulw %[tmp2], 0(%[ptr_j]) \n\t"
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"ulw %[tmp3], 0(%[tr]) \n\t"
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"ulw %[tmp4], 0(%[ti]) \n\t"
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"usw %[tmp1], 0(%[ptr_j]) \n\t"
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"usw %[tmp2], 0(%[ptr_i]) \n\t"
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"usw %[tmp4], 0(%[tr]) \n\t"
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"usw %[tmp3], 0(%[ti]) \n\t"
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"lh %[tmp1], 8(%[pcoeftable_8]) \n\t"
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"lh %[tmp2], 10(%[pcoeftable_8]) \n\t"
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"lh %[tr], 12(%[pcoeftable_8]) \n\t"
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"lh %[ti], 14(%[pcoeftable_8]) \n\t"
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"addu %[ptr_i], %[frfi], %[tmp1] \n\t"
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"addu %[ptr_j], %[frfi], %[tmp2] \n\t"
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"addu %[tr], %[frfi], %[tr] \n\t"
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"addu %[ti], %[frfi], %[ti] \n\t"
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"ulw %[tmp1], 0(%[ptr_i]) \n\t"
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"ulw %[tmp2], 0(%[ptr_j]) \n\t"
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"ulw %[tmp3], 0(%[tr]) \n\t"
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"ulw %[tmp4], 0(%[ti]) \n\t"
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"usw %[tmp1], 0(%[ptr_j]) \n\t"
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"usw %[tmp2], 0(%[ptr_i]) \n\t"
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"usw %[tmp4], 0(%[tr]) \n\t"
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"usw %[tmp3], 0(%[ti]) \n\t"
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"bgtz %[l], 1b \n\t"
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" addiu %[pcoeftable_8], %[pcoeftable_8], 16 \n\t"
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".set pop \n\t"
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: [tmp1] "=&r" (tmp1), [tmp2] "=&r" (tmp2), [ptr_i] "=&r" (ptr_i),
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[ptr_j] "=&r" (ptr_j), [tr] "=&r" (tr), [l] "=&r" (l),
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[tmp3] "=&r" (tmp3), [pcoeftable_8] "+r" (pcoeftable_8),
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[ti] "=&r" (ti), [tmp4] "=&r" (tmp4)
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: [frfi] "r" (frfi)
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: "memory"
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);
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} else if (stages == 7) {
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int16_t* pcoeftable_7 = coefTable_7;
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__asm __volatile (
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".set push \n\t"
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".set noreorder \n\t"
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"addiu %[l], $zero, 56 \n\t"
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"1: \n\t"
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"addiu %[l], %[l], -4 \n\t"
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"lh %[tr], 0(%[pcoeftable_7]) \n\t"
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"lh %[ti], 2(%[pcoeftable_7]) \n\t"
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"lh %[tmp3], 4(%[pcoeftable_7]) \n\t"
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"lh %[tmp4], 6(%[pcoeftable_7]) \n\t"
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"addu %[ptr_i], %[frfi], %[tr] \n\t"
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"addu %[ptr_j], %[frfi], %[ti] \n\t"
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"addu %[tr], %[frfi], %[tmp3] \n\t"
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"addu %[ti], %[frfi], %[tmp4] \n\t"
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"ulw %[tmp1], 0(%[ptr_i]) \n\t"
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"ulw %[tmp2], 0(%[ptr_j]) \n\t"
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"ulw %[tmp3], 0(%[tr]) \n\t"
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"ulw %[tmp4], 0(%[ti]) \n\t"
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"usw %[tmp1], 0(%[ptr_j]) \n\t"
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"usw %[tmp2], 0(%[ptr_i]) \n\t"
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"usw %[tmp4], 0(%[tr]) \n\t"
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"usw %[tmp3], 0(%[ti]) \n\t"
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"lh %[tmp1], 8(%[pcoeftable_7]) \n\t"
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"lh %[tmp2], 10(%[pcoeftable_7]) \n\t"
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"lh %[tr], 12(%[pcoeftable_7]) \n\t"
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"lh %[ti], 14(%[pcoeftable_7]) \n\t"
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"addu %[ptr_i], %[frfi], %[tmp1] \n\t"
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"addu %[ptr_j], %[frfi], %[tmp2] \n\t"
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"addu %[tr], %[frfi], %[tr] \n\t"
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"addu %[ti], %[frfi], %[ti] \n\t"
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"ulw %[tmp1], 0(%[ptr_i]) \n\t"
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"ulw %[tmp2], 0(%[ptr_j]) \n\t"
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"ulw %[tmp3], 0(%[tr]) \n\t"
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"ulw %[tmp4], 0(%[ti]) \n\t"
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"usw %[tmp1], 0(%[ptr_j]) \n\t"
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"usw %[tmp2], 0(%[ptr_i]) \n\t"
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"usw %[tmp4], 0(%[tr]) \n\t"
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"usw %[tmp3], 0(%[ti]) \n\t"
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"bgtz %[l], 1b \n\t"
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" addiu %[pcoeftable_7], %[pcoeftable_7], 16 \n\t"
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".set pop \n\t"
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: [tmp1] "=&r" (tmp1), [tmp2] "=&r" (tmp2), [ptr_i] "=&r" (ptr_i),
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[ptr_j] "=&r" (ptr_j), [ti] "=&r" (ti), [tr] "=&r" (tr),
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[l] "=&r" (l), [pcoeftable_7] "+r" (pcoeftable_7),
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[tmp3] "=&r" (tmp3), [tmp4] "=&r" (tmp4)
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: [frfi] "r" (frfi)
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: "memory"
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);
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}
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}
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